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Home > How To > How about heat dissipation of CORSAIR VENGEANCE 4G DDR3 1600?
How about heat dissipation of CORSAIR VENGEANCE 4G DDR3 1600?

How about heat dissipation of CORSAIR VENGEANCE 4G DDR3 1600?

By  Bradan Pepper 2020-01-03 499 98

There is no need to worry about power consumption, which is different from other hardware in terms of memory. with the upgrading of the technology, the required voltage and power consumption are reduced as the technology is upgraded, while the required voltage and power consumption are reduced. This memory is also equipped with a large area of heat sink. There is no need to worry about thermal power consumption.

Relevant data predict that DDR3 will reduce power consumption by 30% compared with the current DDR2. Of course, we do not need to worry about calorific value. In terms of the balance between bandwidth and power consumption, compared with the existing DDR2-800 products, the power consumption ratios of DDR3-800, 1066 and 1333 are 0.72X, 0.83X and 0.95X, respectively. Not only the memory bandwidth is greatly improved, but also the power performance is better than that of the previous generation.

1, logical Bank number

DDR2 SDRAM has the design of 4Bank and 8Bank, the purpose is to meet the demand of high-capacity chips in the future. DDR3 is likely to start with 2Gb capacity, so the initial logical Bank is 8, and it is ready for the next 16 logical Bank.

2, package (Packages)

DDR3 due to some new functions, so there will be some increase in pins. The 8bit chip is packaged with 78-ball FBGA, the 16bit chip is packaged with 96-ball FBGA, and the DDR2 has three specifications of 60-68-84 ball FBGA package. And the DDR3 must be green and must not contain any harmful substances.

3, burst length (BL,Burst Length)

Because the prefetch of DDR3 is 8 bits, the burst transmission cycle (BL,Burst Length) is also fixed at 8, and for DDR2 and early DDR systems, BL=4 is also commonly used. DDR3 adds a 4-bit Burst Chop (burst mutation mode, that is, a BL=4 read operation and a BL=4 write operation are used to synthesize a BL=8 burst transmission, which can be controlled through the A12 address line. And it should be pointed out that any burst operations will be disabled in DDR3 memory and will not be supported, replaced by more flexible burst transmission control (such as 4bit sequential bursts).

4, addressing timing (Timing)

Just as the number of latency cycles increases after the transformation of DDR2 from DDR, the CL cycle of DDR3 will be higher than that of DDR2. The CL range for DDR2 is generally between 2 and 5, while DDR3 is between 5 and 11, and the design of additional latency (AL) has also changed. The range of AL for DDR2 is 0 to 4, while AL for DDR3 has three options, which are 0, CL-1, and CL-2. In addition, DDR3 also adds a new timing parameter-amp;mdash;- write delay (CWD), which will depend on the specific working frequency.

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