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Home > New Gear > AMD Ryzen 3000, Radeon Navi and EPYC Rome will be launched in Q3 2019
AMD Ryzen 3000, Radeon Navi and EPYC Rome will be launched in Q3 2019

AMD Ryzen 3000, Radeon Navi and EPYC Rome will be launched in Q3 2019

By  Mia Carla 2019-05-20 152 0

Officially, AMD has confirmed that the launch of the Ryzen 3000 and EPYC Rome processors, and the Radeon Navi graphics cards, will occur during the third quarter of 2019. Unfortunately they have not given any specific dates, but taking into account that their announcement will take place on 27 May taking advantage of the start of Computex 2019 everything seems to indicate that they could start to reach the market from mid-June or early July.

In recent years, AMD has gone through very different stages. The launch of the Athlon and Ahtlon 64 processors led the company to live a golden moment. Not only was it able to outperform Intel in gross performance, but it also had the time and resources it needed to start working on its first dual-core processors, the Athlon 64 X2, which were "light years away" from the Pentium Ds.

The situation changed with the arrival of the Conroe architecture, used in the Core 2 Duo and Core 2 Quad. Intel regained the crown of performance it had lost with the Athlon 64 and Athlon 64 X2, and knew how to play their cards to gradually surpass everything that AMD was releasing.

AMD Ryzen 3000

The Phenom II offered excellent value for money, but were behind the first generation Core, based on the Nehalem architecture. To respond to the processors based on the architecture Sandy Bridge AMD bet on the Bulldozer architecture, a line that marked a drastic change compared to the designs that had previously used at silicon level.

Bulldozer opted for a shared resource design in which every two integer cores shared a floating point unit, allowing AMD to create CPUs with eight integer cores and four floating point units. It was an interesting and ambitious idea, but its multi-threaded approach came at a time when quad-core processors were just beginning to be exploited.

This, coupled with its low IPC performance per core, high power consumption and high working temperatures ended up condemning this architecture to failure. Its subsequent revisions, such as Piledriver and Excavator, gave AMD some leeway to develop the architecture that would allow it to return through the big door to the high-performance x86 processor industry, Zen.

Ryzen 3000: what to expect

The Ryzen 3000 processors are based on the Zen 2 architecture, an improved version of the multichip module design we saw in Zen and Zen+. As our regular readers in Zen 2 will know, the CCX units, which integrate four cores each, are simplified and integrated into blocks of two, forming what is known as a chiplet.

In Zen and Zen+ a CCX unit integrates, in addition to the cores and cache, I/O elements and the memory controller. Well, with Zen 2 all these elements are integrated in a dedicated silicon tablet that is located in its own encapsulation, and is manufactured in a 14 nm process.

The chipsets are limited, therefore, to integrate eight cores and the first, second and third level cache memories. This facilitates the leap to the 7 nm process, improves the success rate per wafer, and allows AMD to shape high-performance processors with a large number of cores at a low price.

Ryzen 3000 will therefore have a new design and will use the 7 nm process to improve its efficiency, but these are not the only important new features. As we said at the time AMD plans to increase the number of cores and threads by launching models of 12 cores and 24 threads and 16 cores and 32 threads, the latter being the ones that will shape the new top of the range of the company.

There will also be improvements in gross performance level (IPC), thanks to the introduction of a series of important changes that we summarize below:

▪ Pipeline level enhancements to enhance data delivery and more efficient execution.

▪ Improvements in cache and instructions, and also in the jump prediction system.

▪ Changes to floating point units, which will support 256-bit AVX instructions.

▪ Silicon-level Spectre protection without performance loss.

▪ Lower cache latency, more cache, and higher bandwidth.

▪ Improved Infinity Fabric communication system, resulting in optimal performance with all active cores.

▪ Reduced dependence on RAM speed.

▪ Support of RAM memory to a maximum of 5 GHz.

▪ Performance per watt consumed is halved compared to Zen+.

All this should together allow an average performance improvement of 15% over a Zen+ based chip running at the same frequency and with the same number of cores and threads. If this forecast is met AMD will have reached Intel in gross performance, and with an architecture that, in theory, is considered as "inferior" to the classic monolithic core design.

We remind you that in addition to the configurations of 12 cores and 24 threads and 16 cores and 32 threads we will see models within the Ryzen 3000 series with configurations of 6 cores and 12 threads, and 8 cores and 16 threads.

For its part EPYC Rome will be a line of processors for servers and data centers that will also be based on Zen 2. They will have all the improvements we have mentioned when talking about Ryzen 3000, and will raise the maximum of cores and threads to 64 and 128, respectively.

Radeon Navi: breaking the barriers of GCN architecture

Officially, AMD has confirmed that the launch of the Ryzen 3000 and EPYC Rome processors, and the Radeon Navi graphics cards, will occur during the third quarter of 2019. Unfortunately they have not given any specific dates, but taking into account that their announcement will take place on 27 May taking advantage of the start of Computex 2019 everything seems to indicate that they could start to reach the market from mid-June or early July.

In recent years, AMD has gone through very different stages. The launch of the Athlon and Ahtlon 64 processors led the company to live a golden moment. Not only was it able to outperform Intel in gross performance, but it also had the time and resources it needed to start working on its first dual-core processors, the Athlon 64 X2, which were "light years away" from the Pentium Ds.

The situation changed with the arrival of the Conroe architecture, used in the Core 2 Duo and Core 2 Quad. Intel regained the crown of performance it had lost with the Athlon 64 and Athlon 64 X2, and knew how to play their cards to gradually surpass everything that AMD was releasing.

The Phenom II offered excellent value for money, but were behind the first generation Core, based on the Nehalem architecture. To respond to the processors based on the architecture Sandy Bridge AMD bet on the Bulldozer architecture, a line that marked a drastic change compared to the designs that had previously used at silicon level.

Bulldozer opted for a shared resource design in which every two integer cores shared a floating point unit, allowing AMD to create CPUs with eight integer cores and four floating point units. It was an interesting and ambitious idea, but its multi-threaded approach came at a time when quad-core processors were just beginning to be exploited.

This, coupled with its low IPC performance per core, high power consumption and high working temperatures ended up condemning this architecture to failure. Its subsequent revisions, such as Piledriver and Excavator, gave AMD some leeway to develop the architecture that would allow it to return through the big door to the high-performance x86 processor industry, Zen.

Ryzen 3000: What to Expect

The Ryzen 3000 processors are based on the Zen 2 architecture, an improved version of the multichip module design we saw in Zen and Zen+. As our regular readers in Zen 2 will know, the CCX units, which integrate four cores each, are simplified and integrated into blocks of two, forming what is known as a chiplet.

In Zen and Zen+ a CCX unit integrates, in addition to the cores and cache, I/O elements and the memory controller. Well, with Zen 2 all these elements are integrated in a dedicated silicon tablet that is located in its own encapsulation, and is manufactured in a 14 nm process.

The chipsets are limited, therefore, to integrate eight cores and the first, second and third level cache memories. This facilitates the leap to the 7 nm process, improves the success rate per wafer, and allows AMD to shape high-performance processors with a large number of cores at a low price.

Ryzen 3000 will therefore have a new design and will use the 7 nm process to improve its efficiency, but these are not the only important new features. As we said at the time AMD plans to increase the number of cores and threads by launching models of 12 cores and 24 threads and 16 cores and 32 threads, the latter being the ones that will shape the new top of the range of the company.

There will also be improvements in gross performance level (IPC), thanks to the introduction of a series of important changes that we summarize below:

Pipeline level improvements to enhance data delivery and more efficient execution.

Improvements in cache and instructions, and also in the jump prediction system.

Changes to floating point units, which will support 256-bit AVX instructions.

Silicon-level Spectre protection without performance loss.

Lower cache latency, more cache, and higher bandwidth.

Improved Infinity Fabric communication system, resulting in optimal performance with all active cores.

Reduced dependence on RAM speed.

Support of RAM memory to a maximum of 5 GHz.

Performance per watt consumed is halved compared to Zen+.

All this should allow, overall, an average performance improvement of 15% compared to a chip based on Zen+ operating at the same frequency and with the same number of cores and threads. If this forecast is met AMD will have reached Intel in gross performance, and with an architecture that, in theory, is considered as "".

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