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PCI-SIG announces PCI Express 6.0 specification, up to 256 GB/s

By Adan Flannigan 2019-06-19 725 0

Although we know that AMD is going to be a pioneer in introducing the PCIe 4 bus in its motherboards, the truth is that more advanced specifications already exist, the PCIe 5 already exists as a specification although it is not yet implemented, it is worth remembering that the PCIe 4 specification was presented in 2017, and it is not until now that we will see it physically, PCI-SIG follows the development and launches the PCI Express 6.0 specification.

PCI Express 6.0 will double the bandwidth of the PCIe 5.0 specification up to 64 Gigatransfers per second (GT/s), which should not be confused with Gigabytes per second (GB/s).

Gigatransfers is the measure used by PCI-SIG to determine the gross speed of the uncoded connection, and to understand it you have to know that to send a quantity "x" of encoded bits you have to send a greater quantity without encoding to receive the desired quantity of encoded bits.

All PCIe 3.0 specifications prior to PCIe 3.0 used an 8b/10b encoding ratio, this means that you have to send 10-bit data packets without decoding to receive 8 encoded bits, taking as an example the PCIe 1.0/1.1 that gave 2.5 GT/s in an 8b/10b encoding ratio results in a delivery of 250 MB/s per line, which for example multiplied by 16 gives us the 4GB/s that are capable of offering a PCIe 1.0/1.1 x16 slot.

From PCIe 3 to PCIe 5 a ratio of 128b/130b is used so taking as an example the PCIe 4 that gives 16 GT/s we have 16x(128/130)/8= 1,969 GB/s per line, which gives us the 31,52 GB/s that the PCIe 4 is able to offer in a x16 slot.

Following this formula the PCIe 6.0 specification that gives 64 GT/s should give us 126 GB/s in x16, but thanks to the new PAM-4 coding will reach up to 256 GB/s.

In addition to the increased bandwidth, PCIe 6 will be backward compatible with previous generations and will implement low latency in Forward Error Correction (FEC), or forward error correction.

Finally, here is a table that will simplify all the data related to the speeds of different generations of PCI Express.